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74ABT16543 16-bit latched transceiver with dual enable (3-state) product data replaces 74ABT16543; 74abth16543 dated 1998 feb 27 2002 apr 03 integrated circuits
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2 2002 apr 03 853-1739 27958 features ? two 8-bit octal transceivers with d-type latch ? live insertion/extraction permitted ? power-up 3-state ? power-up reset ? multiple v cc and gnd pins minimize switching noise ? back-to-back registers for storage ? separate controls for data flow in each direction ? output capability: +64 ma/32 ma ? latch-up protection exceeds 500 ma per jedec std 17 ? esd protection exceeds 2000 v per mil std 883 method 3015 and 200 v per machine model description the 74ABT16543 high-performance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. the 74ABT16543 16-bit registered transceiver contains two sets of d-type latches for temporary storage of data flowing in either direction. separate latch enable (nleab , nleba ) and output enable (noeab , noeba ) inputs are provided for each register to permit independent control of data transfer in either direction. the outputs are guaranteed to sink 64 ma. quick reference data symbol parameter conditions t amb = 25 c; gnd = 0 v typical unit t plh t phl propagation delay nax to nbx c l = 50 pf; v cc = 5 v 2.5 2.2 ns c in input capacitance v i = 0 v or v cc 3 pf c i/o i/o capacitance v o = 0 v or v cc; 3-state 7 pf i ccz quiescent su pp ly current outputs disabled; v cc = 5.5 v 550 m a i ccl q u iescent s u ppl y c u rrent outputs low; v cc = 5.5 v 9 ma ordering information packages temperature range order code dwg number 56-pin plastic ssop type iii 40 c to +85 c 74ABT16543dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74ABT16543dgg sot364-1 pin description pin number symbol name and function 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24 1a0 1a7, 2a0 2a7 data inputs/outputs 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40,38, 37, 36, 34, 33 1b0 1b7, 2b0 2b7 data inputs/outputs 1, 56 28, 29 1oeab , 1oeba , 2oeab , 2oeba a-to-b / b-to-a output enable inputs (active-low) 3, 54 26, 31 1eab , 1eba , 2eab , 2eba a-to-b / b-to-a enable inputs (active-low) 2, 55 27, 30 1leab , 1leba , 2leab , 2leba a-to-b / b-to-a latch enable inputs (active-low) 4, 11, 18, 25, 32, 39, 46, 53 gnd ground (0 v) 7, 22, 35, 50 v cc positive supply voltage
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 3 logic symbol (ieee/iec) sh00036 5 6 8 9 10 12 13 14 16 17 19 20 21 23 24 56 1en3 ? 3 5d 1a0 1a1 1a2 1a3 1a4 1a5 1a6 1a7 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 15 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 6d 4 ? ? 911d 12d 10 ? 54 55 1 3 2 29 31 30 28 26 27 1oeba 1eba 1leba 1oeab 1eab 1leab 2oeba 2eba 2leba 2oeab 2eab 2leab g1 1c5 2en4 g2 2c6 7en9 g7 7c11 8en10 g8 8c12 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 27 28 30 29 1oeab 1leab 1eab gnd 1a0 1a1 1a2 1a3 1a4 gnd 1a5 1a6 1a7 2a0 2a2 gnd 2a3 v cc 2a1 2a4 2a5 2a6 2a7 2eab v cc gnd 2leab 2oeab 1oeba 1leba 1eba gnd 1b0 1b1 1b2 1b3 1b4 gnd 1b5 1b6 1b7 2b0 2b2 gnd 2b3 v cc 2b1 2b4 2b5 2b6 2b7 2eba v cc gnd 2leba 2oeba sh00037
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 4 logic symbol 3 54 1eab 1eba 2 1leab 55 1leba 1 1oeab 56 1oeba 26 31 2eab 2eba 27 2leab 30 2leba 28 2oeab 29 2oeba 5 6 10 12 13 14 89 52 51 47 45 44 43 49 48 15 16 20 21 23 24 17 19 42 41 37 36 34 33 40 38 sh00038 1a0 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 functional description the 74ABT16543 contains two sets of eight d-type latches, with separate control pins for each set. using data flow from a to b as an example, when the a-to-b enable (neab ) input and the a-to-b latch enable (nleab ) input are low the a-to-b path is transparent. a subsequent low-to-high transition of the nleab signal puts the a data into the latches where it is stored and the b outputs no longer change with the a inputs. with eab and noeab both low, the 3-state b output buffers are active and display the data present at the outputs of the a latches. control of data flow from b to a is similar, but using the neba , nleba , and noeba inputs. function table inputs outputs status noexx nexx nlexx nax or nbx nbx or nax status h x x x z disabled x h x x z disabled l l l l h l z z disabled + latch l l l l h l h l latch + display l l l l l l h l h l transparent l l h x nc hold h = high voltage level h = high voltage level one set-up time prior to the low-to-high transition of nlexx or nexx (xx = ab or ba) l = low voltage level l = low voltage level one set-up time prior to the low-to-high transition of nlexx or nexx (xx = ab or ba) x = don't care = low-to-high transition of nlexx or nexx (xx = ab or ba) nc= no change z = high impedance or aoffo state
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 5 logic diagram d le q d le q detail a nb0 nb1 na1 nb2 na2 nb3 na3 nb4 na4 nb5 na5 nb6 na6 nb7 na7 detail a x 7 noeab neab nleab noeba neba nleba na0 sh00039 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0 v 18 ma v i dc input voltage 3 1.2 to +7.0 v i ok dc output diode current v o < 0 v 50 ma v out dc output voltage 3 output in off or high state 0.5 to +5.5 v i o dc out p ut current output in low state 128 ma i out dc o u tp u t c u rrent output in high state 64 ma t stg storage temperature range 65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed.
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 6 recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate 0 10 ns/v t amb operating free-air temperature range 40 +85 c dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = 40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5 v; i ik = 18 ma 1.2 1.2 v v cc = 4.5 v; i oh = 3 ma; v i = v il or v ih 2.5 2.9 2.5 v v oh high-level output voltage v cc = 5.0 v; i oh = 3 ma; v i = v il or v ih 3.0 3.4 3.0 v v cc = 4.5 v; i oh = 32 ma; v i = v il or v ih 2.0 2.4 2.0 v v ol low-level output voltage v cc = 4.5 v; i ol = 64 ma; v i = v il or v ih 0.36 0.55 0.55 v v rst power-up output voltage 3 v cc = 5.5 v; i o = 1 ma; v i = gnd or v cc 0.13 0.55 0.55 v i input leakage v cc =55v ; v = gnd or 5 5 v control 001 10 10 m a i i g current v cc = 5 . 5 v ; v i = gnd or 5 . 5 v pins 0 . 01 1 . 0 1 . 0 m a i off power-off leakage current v cc = 0.0 v; v o or v i 4.5 v 2.0 100 100 m a i pu/pd power-up/down 3-state output current 4 v cc = 2.1 v; v o = 0.0 v or v cc ; v i = gnd or v cc ; v oe = don't care 1.0 50 50 m a i ih + i ozh 3-state output high current v cc = 5.5 v; v o = 5.5 v; v i = v il or v ih 1.0 10 10 m a i il + i ozl 3-state output low current v cc = 5.5 v; v o = 0.0 v; v i = v il or v ih 1.0 10 10 m a i cex output high leakage current v cc = 5.5 v; v o = 5.5 v; v i = gnd or v cc 1.0 50 50 m a i o output current 1 v cc = 5.5 v; v o = 2.5 v 50 100 200 50 200 ma i cch v cc = 5.5 v; outputs high, v i = gnd or v cc 0.55 2 2 ma i ccl quiescent su pp ly current v cc = 5.5 v; outputs low, v i = gnd or v cc 9 19 19 ma i ccz quiescent su ly current v cc = 5.5 v; outputs 3state; v i = gnd or v cc 0.55 2 2 ma d i cc additional supply current per input pin 2 v cc = 5.5 v; one input at 3.4 v, other inputs at v cc or gnd 5.0 50 50 m a notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4 v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. this parameter is valid for any v cc between 0 v and 2.1 v, with a transition time of up to 10 msec. from v cc = 2.1 v to v cc = 5 v 10% a transition time of up to 100 m sec is permitted.
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 7 ac characteristics gnd = 0 v, t r = t f = 2.5 ns, c l = 50 pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0 v t amb = 40 c to +85 c v cc = +5.0 v 0.5 v unit min typ max min max t plh t phl propagation delay nax to nbx, nbx to nax 2 1.0 1.0 2.5 2.2 3.3 4.4 1.0 1.0 3.8 5.1 ns t plh t phl propagation delay leba to nax, leab to nbx 1, 2 1.0 1.2 3.1 3.0 4.3 4.8 1.0 1.2 5.2 5.6 ns t pzh t pzl output enable time oeba to nax, oeab to nbx 4 5 1.0 1.1 3.3 3.3 4.3 5.9 1.0 1.1 5.2 7.0 ns t phz t plz output disable time oeba to nax, oeab to nbx 4 5 1.9 1.6 3.5 2.6 5.0 4.2 1.9 1.6 5.7 4.6 ns t pzh t pzl output enable time eba to nax, eab to nbx 4 5 1.0 1.2 3.4 3.4 4.9 6.5 1.0 1.2 6.2 7.8 ns t phz t plz output disable time eba to nax, eab to nbx 4 5 2.0 1.7 3.4 2.6 5.6 5.1 2.0 1.7 6.6 5.4 ns ac setup requirements gnd = 0 v, t r = t f = 2.5 ns, c l = 50 pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0 v t amb = 40 c to +85 c v cc = +5.0 v 0.5 v unit min typ min t s (h) t s (l) set-up time nax to leab , nbx to leba 3 1.5 3.5 0.4 0.1 1.5 3.5 ns t h (h) t h (l) hold time nax to leab , nbx to leba 3 1.5 2.0 0.2 0.3 1.5 2.0 ns t s (h) t s (l) set-up time nax to eab , nbx to eba 3 1.5 3.5 0.2 0.3 1.5 3.5 ns t h (h) t h (l) hold time nax to eab , nbx to eba 3 1.5 2.0 0.3 0.2 1.5 2.0 ns t w (l) latch enable pulse width, low 3 4.0 3.1 4.0 ns ac waveforms v m = 1.5 v, v in = gnd to 3.0 v v in v m t phl t plh v m v m v m v out sh00040 waveform 1. propagation delay for inverting output v m t plh t phl v m v m v m v in v out sh00041 waveform 2. propagation delay for non-inverting output
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 8 ac waveforms (continued) v m = 1.5 v, v in = gnd to 3.0 v v m nax, nbx v m v m v m v m v m nleab , nleba , neab , neba t s (h) t h (h) t s (l) t h (l) t w (l) note: the shaded areas indicate when the input is permitted to change for predictable output performance. sh00042 waveform 3. data setup and hold times and latch enable pulse width noeab , noeba , neab , neba v m t pzh t phz 0v v oh 0.3v v m v m nax, nbx v oh sh00043 waveform 4. 3-state output enable time to high level and output disable time from high level t pzl t plz v ol +0.3v v m v m v m noeab , noeba , neab , neba nax, nbx v ol sh00044 waveform 5. 3-state output enable time to low level and output disable time from low level test circuit and waveforms pulse generator r t v in d.u.t. v out r l v cc r l 7.0v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family amplitude rep. rate t w t r t f 74abt/h16 3.0v 1mhz 500ns 2.5ns 2.5ns switch position test switch t plz closed t pzl closed all other open sa00018 c l
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 9 ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 10 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 11 notes
philips semiconductors product data 74ABT16543 16-bit latched transceiver with dual enable (3-state) 2002 apr 03 12 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 04-02 document order number: 9397 750 09692

data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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